1. Field of the Invention
The present invention relates to a semiconductor device employing a field-effect transistor having a gate electrode with a comb-shaped structure and, more particularly, to the semiconductor device having a structure designed to minimize a reduction in gain in a high frequency band not lower than the microwave band.
2. Description of the Prior Art
An example of the prior art field-effect transistor having a gate electrode with a comb-shaped structure is shown in FIG. 19. Referring to FIG. 19, the field-effect transistor (or the FET) 200 to be used at a high frequency higher than the microwave band is provided with a gate electrode 201 having a comb-shaped structure, a drain electrode 202 similarly having a comb-shaped structure and an array of source electrodes 204 that are connected together by way of an air bridge 203. The source electrodes located at both ends of the array of the source electrodes 204 are connected to corresponding grounding electrodes 206a and 206b grounded by way of via holes 205a and 205b.
A semiconductor chip having the FET 200 formed thereon has test electrodes 210a, 210b, 220a and 220b formed thereon that are used during a on-wafer examination to determine operating characteristics of the FET 200 on the wafer. The test electrodes 210a, 210b, 220a and 220b are connected in correspondence with test pads 211a, 211b, 221a and 221b, respectively, that are used for connection with a test machine during the on-wafer examination.
The test pads 211a, 211b, 221a and 221b are connected to the ground through the corresponding via holes 212a, 212b, 222a and 222b. A high frequency signal inputted from an external circuit by way of a connection pad 213, formed between the test pads 211a and 211b, during the on-wafer examination is inputted to the gate electrode 201 through a signal line 214. The high frequency signal inputted is amplified by the FET 200, and the amplified high frequency signal is outputted from a connection pad 223, formed between the test pads 221a and 221b, through the drain electrode 202 by way of a signal line 224. The connection pads 213 and 223 are connected with an external circuit when the FET 200 available as a commercial product is used.
In the above construction, the field-effect transistor 200 has a parasitic impedance comprised of a source resistance Rs and a parasitic inductance (referred to as a source inductance hereinafter) Ls on the source electrode side, which are generated due to the structure of the source electrodes, the grounding electrodes and the via holes.
FIG. 20 is a graph showing a relation between a unit gate width Wgu and a total gate width Wgt of the gate electrode 201 with respect to the source inductance Ls of the FET 200 shown in FIG. 19. FIG. 20 shows the fact that the source inductance Ls increases according to a reduction in the unit gate width Wgu and an increase in the total gate width Wgt.
On the other hand, FIG. 21 illustrates an equivalent circuit of the FET 200 during the on-wafer examination. As shown therein, during the on-wafer examination, in addition to the source inductance Ls, a parasitic impedance Lt is also generated due to the structure of the test electrodes 210a, 210b, 220a and 220b and the via holes 212a, 212b, 222a and 222b. Reference character Rs used in FIG. 21 represents a source resistance of the FET 200.
As described above, there has been the conventional problem that the gain of the FET 200 reduces to deteriorate the high-frequency characteristics because of the increase in frequency and the increase in the parasitic impedance accompanying the increase in the total gate width of the FET 200. This has resulted in a difficulty in obtaining both a high gain and a large output power in the high frequency band with the prior art FET 200 having the comb-shaped gate structure.
It is to be noted that a field-effect transistor in which the source inductance of the via holes is reduced by arranging a plurality of via holes in a source electrode pad is disclosed in, for example, Japanese Patent Laid-Open Publication No. 8-274116.